An FPGA-based hardware accelerator for simulating spatiotemporal neurons

Simulating spatiotemporal neurons is fundamental to understanding motion detection mechanisms in the primary
visual cortex and cloning these mechanisms in digital systems. We present a hardware accelerator that leverages the parallelism
of a modern Field Programmable Gate Array (FPGA) to increase the speed of spatiotemporal computations by 12 orders of
magnitude for video framebuffer sizes up to 128×128×25 pixels. The accelerator is primarily intended for running simulations
of large spatiotemporal neuron populations but can also be used in computer vision applications that require high-speed spatiotemporal processing such as realtime motion detection.
TarawnehRead2014.pdf
File Size0.5 MiB
DateAugust 8, 2015
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AuthorTarawneh G, Read JCA